In the computer industry, memory devices and methods for the storage of information have long been of critical importance. Accordingly, the improvement of semiconductor technology, and the memory elements thereby produced, is of significant value.
The term EEPROM is used for memory elements which have the ability to be erased and rewritten after fabrication. These memory cells are generally based on MOS technology and utilize a floating gate structure. In such memory cells, an electrical charge is transferred or written onto the electrically isolated floating gate thus controlling the threshold voltage of the device. A read operation differentiates between the impedance presented by a charged gate and an uncharged gate. Thus, a charged gate may be used to represent one (binary) state of the cell, an uncharged gate the other. To reverse the state of the cell, the charge is transferred off the floating gate or erased.
Typically, an EEPROM is comprised of multiple memory cells in an array or matrix-type structure, i.e. it is fabricated as a multiplicity of parallel bit or column lines which are generally perpendicular to a multiplicity of parallel word or row lines. In such an array, a single memory cell may be identified by the intersection of a specified column line with a specified row line. That cell may be programmed or erased by applying appropriate voltages to a particular column and a particular row line. EEPROMs in which erasure may be performed over the entire array or matrix of cells are referred to as flash EEPROMs. Bulk erases of this nature have an advantage in that it permits smaller cell size.
Numerous solutions have been proposed to facilitate the programming (or writing) and erasing of floating gates.
Some solutions focus on the structure or design of the memory cell. For example, one such design uses a single control gate separated from the floating gate by an insulating layer. Writing is accomplished by biasing the control gate sufficiently positive that the electron flow is induced from the floating gate to the control gate. The floating gate accordingly accumulates positive charge. To erase, the control gate is ramped negative so that the floating gate accumulates negative charge. (This approach is discussed in Lee, A New approach for the Floating Gate MOS Nonvolatile Memory, Applied Physics Letters, Vol. 31, No. 7, October 1977, pp. 475-476.)
Another common design uses both a programming gate and an erase gate. In cells based on this type of design, the floating gate is programmed by inducing electron flow from the programming gate to the control gate and erased by inducing electron flow from the floating gate to the erasure gate. (This design is exemplified in U.S. Pat. No. 4314265.)
Other solutions focus on the methods of writing or erasing the floating gate. The charge transfer mechanisms most frequently used for these purposes are hot electron injection (typically from avalanche breakdown although hot electron injection may also result from channel hot electrons) or Fowler-Nordheim tunneling.